Impedance matching circuits and interface circuits
US10348271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Jan 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018564
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.