Summing circuit
US10348284B2 · kind B2 · utility
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2References
13Claims
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Key dates
| Filing date | Sep 25, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.