Frequency division correction circuit, reception circuit, and integrated circuit
US10348316B2 · kind B2 · utility
5Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.