Multi-processor core device with MBIST
US10352998B2 · kind B2 · utility
1Cited by
2References
24Claims
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Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Nov 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.