Rapid scan testing of integrated circuit chips
US10353001B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.