Display panel and manufacturing method thereof
US10353251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Jan 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/121
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.