Current in-rush mitigation for power-up of embedded memories
US10353447B2 · kind B2 · utility
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9References
16Claims
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Key dates
| Filing date | Mar 3, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.