Analog fault simulation control with multiple circuit representations
US10353789B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Jan 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application discloses a computing system to identify multiple views of cells in a circuit design for selective utilization during analog fault simulation of the circuit design. The views of the cells can include two or more of macromodel design views, schematic design views, or extracted design views that includes parasitic elements extracted from a physical layout of the circuit design. The computing system can prompt generation of multiple netlists, each netlist generated based on a different combination of the identified views of the cells in the circuit design, or a list of macromodels with pin accurate subcircuit wrappers, parse and organize the cells in each netlist or the list of macromodels, identify one of the cells to inject with a defect, and selectively simulate portions from a plurality of the netlists based, at least in part, on the identified one of the cells to inject with the defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.