Process for improving capacitance extraction performance
US10354041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.