Semiconductor device and imaging device
US10355039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.