Polycrystalline silicon thin film transistor and method of fabricating the same, and display apparatus
US10355107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.