Patent · US Active

Clock gating circuit

US10355674B2 · kind B2 · utility

2Cited by

7References

23Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Anil Kumar Baratam · Bengaluru, IN
Nruthya Nagesh Prabhu · Bengaluru, IN
Yves Thomas Laplanche · Valbonne, FR

Key dates

Filing date	Jul 24, 2017
Grant date	Jul 16, 2019
Priority date	—
Expiry date	Aug 31, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/6872
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.