High-efficiency frequency doubler with a compensated transformer-based input balun
US10355678B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosed embodiments relate to the design of a high-speed frequency doubler circuit. During operation, the circuit uses a transformer-based balun to convert a single-ended input signal into a differential signal, wherein the transformer-based balun includes a transformer with a primary coil, which receives the single-ended input signal, and a secondary coil, which produces the differential signal. The transformer also includes a central compensation capacitor coupled between a center tap of the secondary coil and ground, wherein the central compensation capacitor acts to suppress common-mode components in the differential signal. Next, the circuit uses a pseudo-differential amplifier to convert the differential signal into a single-ended output signal, which has double the frequency of the single-ended input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.