Equalization of sub-DAC frequency response misalignments in time-interleaved high-speed digital to analog converters
US10355706B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. hm(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eqm are determined from Eqm(F)=T(F)/hm(F), to form equalizing frequency responses. Sets of equalizing coefficients Cm(p) pursuant to discrete Fourier transforms on Eqm(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients Cm(p).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.