Pseudowire clock recovery
US10355799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0673
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Clock synchronization in a network includes receiving, by a slave network device from a master network device via at least a intervening network device, a timing packet comprising a transmission timestamp and a residence time. The transmission timestamp is based on a master clock of the master network device. The residence time corresponds to a delay of the timing packet traversing the intervening device. Clock synchronization in a network further includes generating, by the slave network device in response to receiving the timing packet, a receiving timestamp based on a slave clock of the slave network device, and generating, based at least on the transmission timestamp, the residence time, and the receiving timestamp, a time difference between the master clock and the slave clock. Clock synchronization in a network further includes synchronizing, based at least on the time difference, the master clock and the slave clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.