Patent · US Active

Scalable transform hardware architecture with improved transpose buffer

US10356440B2 · kind B2 · utility

1Cited by
18References
29Claims
0Family size

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Inventors

Key dates

Filing dateOct 1, 2014
Grant dateJul 16, 2019
Priority date—
Expiry dateFeb 2, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04N19/91
  • WIPO fieldAudio-visual technology
  • WIPO sectorElectrical engineering

Abstract

As the quality and quantity of shared video content increases, video encoding standards and techniques are being developed and improved to reduce bandwidth consumption over telecommunication and other networks. One such technique for compressing videos involves transforming image data into an alternate, encoding-friendly domain (e.g., by a two-dimensional discrete cosine transform). Transform modules may be implemented to perform these transformations, which may occur during both video encoding and decoding processes. Provided are exemplary techniques for improving the efficiency and performance of transform module implementations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.