Patent · US Active

Circuit arrangement for clock synchronization

US10356736B2 · kind B2 · utility

1Cited by

3References

16Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Steffen Reinhardt · Pforzheim, DE
Peter Bode · Unterhaching, DE

Key dates

Filing date	May 22, 2017
Grant date	Jul 16, 2019
Priority date	—
Expiry date	May 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH04W56/0055
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.