Biasing current regularization loop stabilization
US10359800B2 · kind B2 · utility
1Cited by
1References
22Claims
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/294
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.