Low latency system having high availability computer architecture
US10360118B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Dec 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1662
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for processing external inbound messages with failover protection having low latency and high availability. The system includes a primary data processing host and a secondary data processing host. Each of the primary and secondary data processing hosts include a memory space shared by separate data processing components. The memory spaces of the primary and secondary data processing hosts are synchronized using a low-latency remote direct memory access. The synchronization is performed on data items stored in the memory spaces associated with one inbound message at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.