Design-aware pattern density control in directed self-assembly graphoepitaxy process
US10361116B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 20, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.