Method and structure for mandrel and spacer patterning
US10361286B2 · kind B2 · utility
4Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jun 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC manufacturing method includes forming first mandrels and second mandrels over a substrate; and forming first spacers on sidewalls of the first mandrels and second spacers on sidewalls of the second mandrels. Each of the first and second spacers has a loop structure with two curvy portions connected by two lines. The method further includes removing the first and second mandrels; and removing the curvy portions from each of the first spacers without removing the curvy portions from the second spacers. The second spacers are used for monitoring variations of the IC fabrication processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.