High voltage MOSFET devices and methods of making the devices
US10361302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.