Sidewall metal spacers for forming metal gates in quantum devices
US10361353B2 · kind B2 · utility
1Cited by
3References
24Claims
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Key dates
| Filing date | Feb 8, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Feb 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.