Decoding of non-binary LDPC codes
US10361723B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 7, 2015 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1171
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.