Error correction encoder, error correction decoder, and optical communication device including the same
US10361727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first parities by performing a first error correction encoding on each of the input words, an interleaver for generating interleaved words by performing interleaving on the input words, a second encoder for generating a plurality of second parities by performing a second error correction encoding on each of the interleaved words, output nodes for outputting each of the input words, first parity output nodes for outputting the first parities, and second parity output nodes for outputting the second parities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.