Fault detection in a low voltage differential signaling (LVDS) system
US10361732B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/18
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.