Memory transaction-level modeling method and system
US10365829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.