Machine perception and dense algorithm integrated circuit
US10365860B1 · kind B1 · utility
4Cited by
10References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 1, 2019 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.