Memory interleave system and method therefor
US10366005B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | May 20, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Jun 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.