System for and method of manufacturing a layout design of an integrated circuit
US10366200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Nov 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.