Integrated circuits and devices with interleaved transistor elements, and methods of their fabrication
US10366986B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/105
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.