Ramp based clock synchronization for stackable circuits
US10367484B2 · kind B2 · utility
3Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.