Array substrate, method of manufacturing the same, and display device
US10371997B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Oct 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.