Thread importance based processor core partitioning
US10372494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each processor core in a device supports various different frequency ranges and/or energy performance preferences, and can operate to run threads at any one of those different frequency ranges and/or energy performance preferences. Processor cores are partitioned into different groups, each group running at different frequency ranges and/or energy performance preferences. Threads in the device are assigned one of multiple importance levels and scheduled to run on a processor core in a particular group based on the importance level of the thread. Lower importance level threads are scheduled to run in a group that is more power efficient, and higher importance level threads are scheduled to run in a group that is higher performance. The group that a processor core is part of can change during operation of the device based on the needs of the device and/or applications running on the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.