Register allocation system
US10372500B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | May 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.