Compute architecture in a memory device of distributed computing system
US10372506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method performed by a processing module embedded in a solid state memory device begins by receiving at least one partial task related to a group of slices of contiguous data, and slices of the group of slices of contiguous data to produce received slices. The received slices are random access stored in the solid state memory device, and the processing module decides whether to execute the at least one partial task. In response to a positive determination, a portion of the received slices are random access retrieved, and the at least one partial task is executed using the portion of the received slices to generate a partial result. The partial result is random access stored in the solid state memory device; and the processing module facilitates dispersed storage of the partial result in a distributed storage task network (DSTN).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.