FPGA mismatched packet stop for a safety system
US10372579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Sep 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.