In-memory shared data reuse replacement and caching
US10372677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Jan 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache management system for managing a plurality of intermediate data includes a processor and a memory having stored thereon instructions that cause the processor to perform identifying a new intermediate data to be accessed, loading the intermediate data from the memory in response to identifying the new intermediate data as one of the plurality of intermediate data, in response to not identifying the new intermediate data as one of the plurality of intermediate data, selecting a set of victim intermediate data to evict from the memory based on a plurality of scores associated with respective ones of the plurality of intermediate data, the scores being based on a score table, evicting the set of victim intermediate data from the memory, updating the score table based on the set of victim intermediate data, and adding the new intermediate data to the plurality of intermediate data stored in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.