Error resilient digital signal processing device
US10372868B2 · kind B2 · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2015 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.