Semiconductor package structure and method of manufacturing the same
US10373931B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Apr 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package structure is provided. A stacked structure formed over the carrier substrate is provided, wherein the stacked structure has a channel with an opening. The stacked structure is immersed into a fluidic molding material to render the fluidic molding material flow into the channel through the openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.