Semiconductor memory devices including separate upper and lower bit line spacers
US10373960B2 · kind B2 · utility
7Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.