Field effect transistor with controllable resistance
US10374041B2 · kind B2 · utility
4Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.