Differential amplifier with complementary unit structure
US10374554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45508
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.