Low power retention flip-flop with level-sensitive scan circuitry
US10374584B1 · kind B1 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2018 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.