Read tail latency reduction
US10374634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An individual latency indicator is determined for each Data Storage Device (DSD) or memory portion of a DSD storing one or more erasure coded shards generated from an erasure coding on initial data. Each individual latency indicator is associated with a latency in retrieving an erasure coded shard stored in a respective DSD or memory portion. At least one collective latency indicator is determined using determined individual latency indicators, with the at least one collective latency indicator being associated with a latency in retrieving multiple erasure coded shards. The at least one collective latency indicator is compared to a latency limit, and a subset of erasure coded shards is selected to retrieve based on the comparison of the at least one collective latency indicator to the latency limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.