Clock phase adjustment using clock and data recovery scheme
US10374785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.