Processor core to coprocessor interface with FIFO semantics
US10380058B2 · kind B2 · utility
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Key dates
| Filing date | Sep 6, 2016 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | May 26, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.