Dual I2C and SPI slave for FPGA and ASIC implementation
US10380061B2 · kind B2 · utility
1Cited by
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12Claims
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Key dates
| Filing date | Dec 26, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.