Patent · US Active

Analog design tool, cell set, and related methods, systems and equipment

US10380307B1 · kind B1 · utility

1Cited by

23References

15Claims

0Family size

Assignee

Silicon Technologies, Inc. · US

Inventors

Thomas L. Wolf · Webster, US
Kent F. Smith · Jacksonville, US
Tracy Johancsik · Murray, US
Kyler C. Fillerup · Orem, US
Thomas Wolf · Barsinghausen, DE

Key dates

Filing date	Mar 29, 2017
Grant date	Aug 13, 2019
Priority date	—
Expiry date	May 17, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for designing an semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.