Accelerator for k-means clustering with memristor crossbars
US10380386B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A crossbar array includes a number of memory elements. A vector input register has N voltage inputs to the crossbar array. A vector output register has M voltage outputs from the crossbar array. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A clustering processor is electronically coupled to the ADC and to the DAC. The clustering processor is configured to program columns of the crossbar array with a set of k cluster center values; apply voltages to rows of the crossbar array where the applied voltages represent a set of data values; and determine a minimum distance of each data value to each k cluster center values based on the voltage output from the output register of each of the plurality of the programmed columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.